De-Sheng Chen

Full-Time Associate Professor

  • dschen@fcu.edu.tw

Ph.D., Electrical Engineering, Northwestern University, U.S.A.

Research areas

VLSI CAD, Computer Vision, Image Processing

Courses

Digital System Design, Logic Design, Signal Processing

  • Profile
  • Publications
  • Research & Teaching
Profile

FCU Positions

  • Associate Professor, Department of Information Engineering and Computer Science
  • Assistant Professor, Department of Information Engineering and Computer Science
  • Secretary, Department of Information Engineering and Computer Science
Publications

Journal Articles

  • Guo-Ming Fang, Jim-Min Lin, Zeng-Wei Hong, De-Sheng Chen, and Wei-Tsong Lee, "Constructing Service-Oriented Integrated EDA Environment with Agent Technology," Journal of Internet Technology,12/6, PP. 949~967, 2011-11. (SCI,EI)
  • De-Sheng Chen*, Chang-Tzu Lin, Yi-Wen Wang, and Ching-Hwa Cheng, "Constrained Floorplanning for Modern SoC Design," Journal of Cybernetics and Systems, Vol. 1, No. 1, PP. 27~39, 2008-08.
  • De-Sheng Chen, Chang-Tzu Lin, Yi-Wen Wang, and Ching-Hwa Cheng, "Fixed-Outline Floorplanning Using Robust Evolutionary Search," Engineering Applications of Artificial Intelligence, 20, PP. 821~830, 2007-06. (SCI,EI)
  • De-Sheng Chen, Chang-Tzu Lin and Yi-Wen Wang, "A Robust Genetic Algorithm for Rectangle Packing Problem," Journal of Combinatorial Optimization (JOCO), Vol. 12, 2006-05. (SCI,EI)
  • Chang-Tzu Lin, De-Sheng Chen and Yi-Wen Wang, "VLSI Floorplanning with Boundary Constraints Using Generalized Polish Expression," Journal of the Chinese Institute of Engineers (JCIE), Vol.29, No.3, PP. 383~389, 2006-05. (SCI,EI)
  • Chang-Tzu Lin, De-Sheng Chen and Yi-Wen Wang, "Modern Floorplanning with Boundary and Fixed-Outline Constraints via Genetic Clustering Algorithm," Journal of Circuits, Systems, and Computers, JCSC,Vol. 15, No. 1, PP. 107~127, 2006-02. (SCI,EI)

 

Conference Papers

  • Hong-Son Vu, Jia-Xian Guo, Kuan-Hung Chen, Shu-Jui Hsieh, and De-Sheng, "A Real-Time Moving Objects Detection and Classification Approach for Static Cameras," 2016 International Conference on Consumer , p.258 - p.259 , 2016-05. National Chi Nan University.
  • C. H. Lin, B. C. Yang, C. B. Duanmu, B. W. Chen, D. S. Chen, and Y. Wang, "Neural Cryptography for Secure Voice Communication using Custom Instructions," Int'l Conf. Embedded Systems and Applications, p.57 - p.61 , 2015-07. Las Vegas, Nevada.
  • Huan-Teng Li, De-Sheng Chen, Yi-Wen Wang, "A Predict Policy Method for Word-Based Montgomery Modular Multiplication," 2012 VLSI/CAD Symposium , 2012-08. Kenting, Taiwan.
  • Che-Ming Chang, De-Sheng Chen, Y-Wen Wang, "A High-throughput Deblocking Filter With New Filtering Schedule," 2012 International Conference on Electronics, Communication and Computer Science , 2012-06. Naning, China.
  • C. Hung, H. Lin, D. Chen, Y. Wang, "ASIP Instruction Selection with the Encoding-Space Constraint for High Performance," International Workshop on Highly-Efficient Accelerators and Reconfigurable Technologies(HEART 2012) , 2012-05. Okinawa, Japan.
  • Ginhsuan Li, Chiuyun Hung, De-Sheng Chen, and Yiwen Wang*, "Application-Specific Instruction sets Processor with Implicit Registers to Improve Register Bandwidth," World Academy of Science, Engineering and Technology , 2011-06. Paris, France.
  • De-Sheng Chen*, Po-Yu Chen, Yi-Wen Wang, "Hardware/Software Co-Design of NLMS Adaptive Filters on FPGA," International Symposium on Consumer Electronics , 2011-06. Singapore.
  • Chengpin Tseng, Chiuyun Hung, De-Sheng Chen, Kuei-Chung Chang and Yi-wen Wang*, "Application Specific Instruction set Exploration on VLIW Architectures," International Conference on Embedded Systems and Applications , 2010-07. Las Vegas Nevada, USA.
  • De-Sheng Chen*, Kui-Shun Chou, Yi-Wen Wang, "A New Block-Based Stochastic Adaptive Algorithm for Sparse Echo Cancellation," The International Conference on Signal Processing Systems , 2010-07. Dalian, China.
  • Guo-Ming Fang, Jim-Min Lin, Zeng-Wei Hong, De-Sheng Chen, "An Agent-Based Workflow System for Assisting in IC Design," The 1st Asian Conference on Intelligent Information and Database Systems (ACIIDS 2009) , 351-355 , 2009-04. Dong Hoi, Vietnam.
  • Chijie Lin, Jiying Wu, Jerung Shiu, De-Sheng Chen, and Yiwen Wang*, "Performance Improvement using Application-Specific Instructions under Hardware Constraints," International Conference on embedded Software and Systems , 2008-07. Chengdu, China.
  • Jiying Wu, Chijie Lin, De-Sheng Chen, Yiwen Wang*, "Memory Models for an Application-Specific Instruction-set Processor Design Flow," International Conference on Embedded Software and Systems , 2008-07. Chengdu, China.
  • Chang-Tzu Lin, Tai-Wei Kung, De-Sheng Chen*, Yi-Wen Wang, and Ching-Hwa Cheng, "Noise-Aware Floorplanning for Fast Power Supply Network Design," International Symposium on Circuits and Systems, 2007-05. New Orlean, U.S.A.
  • Wei-Chih Shen, Jyun-Sian Jhou, Ching-Hwa Cheng, De-Sheng Che, "PIPD: Power Integrity Path Delay Analysis Tool," International Computer Symposium , 78-81 , 2006-12. Taiwan, Taipei.
  • Chih-Liang Chen, Hsiang-Hui Huang, Ching-Hwa Cheng, De-Sheng Chen, "Diagnose the Failure Power-Switch within Power Gating Circuit," The 17th VLSI Design/CAD symposium , 2006-08. Hualien, Taiwan.
  • Chang-Tzu Lin, Tai-Wei Kung, De-Sheng Chen, Yi-Wen Wang, and Ching-Hwa Cheng, "A Novel Design Methodology for SI Aware Floorplanning Designs," 17th VLSI Design/CAD Symposium , 2006-08. Hualien, Taiwan.
  • Shengjyi Yang, Chijie Lin, Chiuyun Hung, Jiying Wu, Jiawei Chang, De-Sheng Chen, and Yi-Wen Wang,"Automatic Application-Specific Instruction Generation for SOC Processors," 17th VLSI Design/CAD Symposium , 2006-08. Hualien, Taiwan.
  • Ching-Hwa Cheng, De-Sheng Chen, Wen-Jui Chang, Chih-Liang Chen, "All-Digital Built-in Circuit Delay Tester," 15th IEEE North Atlantic Test Workshop , 120-129 , 2006-05. USA.
  • Hsin-Hsien Ho, Chang-Tzu Lin, De-Sheng Chen, and Yi-Wen Wang, "Multilevel Genetic Placement Algorithm for Large-Scale Mixed-Size SOC Designs," The 16th VLSI Design/CAD Symposium , . , 2005-08. Hualien, Taiwan.
  • 34. Chih-Liang Chen, Hsiang-Hui Huang, Ching-Hwa Cheng, De-Sheng Chen, "A Delay/Power Compromise Mixed Static/Domino Circuit Synthesizer," The 17th VLSI Design/CAD symposium , 2005-08. Hua-Lian.
  • Hsin-Hsien Ho, Chang-Tzu Lin, De-Sheng Chen, Yi-Wen Wang, "Modern Floorplanning with Abutment and Fixed-Outline Constraints," ISCAS 2005 , pp.6214-6217 , 2005-05. Kobe, Japan.
  • Chang-Tzu Lin, De-Sheng Chen, Yi-Wen Wang, Po-Shu Shih, and Ying-Ren Xhao, "Fixed-Outline Floorplanning with Abutment Constraints," The 15th VLSI Design/CAD Symposium , . , 2004-08. Kenting, Taiwan.
  • Ching-Chung Hu; De-Sheng Chen; Yi-Wen Wang, "Fast multilevel floorplanning for large scale modules,"the 2004 International Symposium on Circuits and Systems , Volume: 5 , 23-26 , 2004-05. 加拿大溫哥華.
  • Chang-Tzu Lin, De-Sheng Chen, and Yi-Wen Wang, "Robust Fixed-outline Floorplanning Through Evolutionary Search," IEEE/ACM 2004 Asia and South Pacific Design Automation Conference , pp 42~44 , 2004-01. Yokohama, Japan.
  • Chang-Tzu Lin, De-Sheng Chen, and Yi-Wen Wang, "Robust Fixed-outline Floorplanning Through Evolutionary Search," 2003 VLSI Design/CAD Symposium , pp 9~12 , 2003-08. 花蓮.
  • De-Sheng Chen, Chang-Tzu Lin, and Yi-Wen Wang, "Non-Slicing Floorplans with Boundary Constraints Using Generalized Polished Expression," IEEE/ACM 2003 Asia and South Pacific Design Automation Conference 2003 , pp 342-345 , 2003-01. 日本、九州.
  • W.-R. Lin、M.-H. Fan、C.-H. Huang, Y.-C. Chung, and D.-S. Chen, "Synthesizing VHDL Programs from Tensor Product Formulas," 2002 International Conference on VLSI , 134~140 , 2002-06. Las Vegas, Nevada, USA.
  • Chang-Tzu Lin、De-Sheng Chen、Yi-Wen Wang, "An Efficient Gentic Algorithm for Slicing Floorplan Area Optimizition," IEEE ISCAS 2002 , 879~882 , 2002-05. USA、Phoenix.
  • Zen-Wei Hong、Jim-Min Lin、Hewijin C. Jiau、De-Sheng Chen, "DSIAS: A Software Architecture Style for Distributed Software Integration Systems," IEEE Compsac 2001 , pp 291~296 , 2001-10. Chicago, USA.
  • Chang-Tzu Lin、De-Sheng Chen、Yi-Wen Wang、I-Tsung Chen, "A Fast Evolutational Algorithm for Slicing Floorplans," Proceedings of Proceedings of the 12th VLSI Design/CAD Symposium , CD-ROM , 2001-08. Hsin-Chu Taiwan.
  • De-Sheng Chen, Dar-Chang Juang, Jyuo-Min Shyu, and Ching-Yuang Wu, "A Low-power 1.2GHz 0.35um CMOS PLL," Proceedings of AP-ASIC 2000 , 99-102 , 2000-08. .
  • S. W. Chen, C. W. Hsu, Y. W. Wang, D. S. Chen, C. T. Lin, and S. F. Hwang, "VLSI implementations of a multicasting shared buffer for QoS multimedia networks," Proceedings of the 11th VLSI Design/CAD Symposium , pp. 217-220 , 2000-08.

 

Books & Technical Reports

  • 專業書籍 王壘, 袁世一, 王益文, 陳德生 ARM Cortex-M3 32位元微控制器原理與應用 全華圖書 中華民國 2017-04-01 328 原著 ISBN:9789864633616
Research & Teaching

Teaching at ISTM in Fall 2018/Spring 2019

  • Digital System Design (FCU-Purdue Program Year 2)

 

Research Interests

  • VLSI CAD
  • Computer Vision
  • Image Processing